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Testchip tape-out (1)

Layout engineer task during tape-out stage as follow:
1) LVS check.
2) DRC check. If wholechip have awaived DRC, layout engineer must confirm with Designer.
3)ERC check.
4) Antenna check.
5) ESD check. (Careful check IO Pad).
6) Layer ID.
7) Laser Marker.
8) LOGO.

posted on 2008-05-14 21:28 洪七 阅读(297) 评论(0)  编辑 收藏 引用 所属分类: 技术

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