“集成”人生

集成电路学习心得与个人生活流水

统计

留言簿(1)

链接

阅读排行榜

评论排行榜

Testchip tape-out (1)

Layout engineer task during tape-out stage as follow:
1) LVS check.
2) DRC check. If wholechip have awaived DRC, layout engineer must confirm with Designer.
3)ERC check.
4) Antenna check.
5) ESD check. (Careful check IO Pad).
6) Layer ID.
7) Laser Marker.
8) LOGO.

posted on 2008-05-14 21:28 洪七 阅读(295) 评论(0)  编辑 收藏 引用 所属分类: 技术

只有注册用户登录后才能发表评论。